Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm gate length. We have observed that for low-temperature analog operation, high-k gate dielectric is not a viable option at this gate length, as the intrinsic dc gain (A
_V0
) decreases with increase in dielectric constant of the gate dielectric because of a pronounced increase in fringe-induced barrier lowering. On the other hand, dual-k spacer-based underlap FinFET is a promising candidate in improving critical analog figures of merit (FOM), such as intrinsic dc gain (A
_V0
), cutoff frequency (f
_T
), and maximum oscillation frequency (f
_max
) as the temperature is reduced. More so, the percentage increase in FOM of dual-k FinFET is enhanced at lower temperature as well as at lower gate length. Therefore, dual-k spacer underlap FinFET can be a possible solution for further device scaling at low-temperature environment.