Design-based thermal simulation methodology for ball grid array packages

Numerical simulation of steady-state thermal behaviour of ball grid array (BGA) electronic packages can be greatly eased through the simplification of small-scale geometric features. Such features include plated through-holes (PTHs), vias, controlled collapse chip connection (C4) solder joints, extended evaporated eutectic (E3) solder joints, controlled collapse chip connection carrier (C5) solder joints, and printed wiring board (PWB) copper trace patterns. Accurate and timely system-level modeling relies on simplifying the geometric representation of these features while capturing their thermal effects. A strict, single-pass modeling methodology based solely on design data and readily available bulk material properties is presented.