Impact of replacing Sn-Ag bumps with Cu pillars on the BEoL Cu/Low-k fracture under reflow - a computational study

Replacing Silicon Dioxide (SiO
₂
) with low-k and ultralow-k (ULK), as a dielectric, in the Back-End-Of-Line (BEoL) has allowed the trend of miniaturization and convergence to continue. Although using low-k and ULK greatly increases the device performance, being mechanically weak these dielectric materials pose a serious challenge from the reliability standpoint. Delamination along the metal-dielectric interfaces and crack propagation in the dielectric layers has been widely observed during cooling from higher temperatures and thermal excursions. Moreover, as scaling of components continues, higher density interconnects and pitch <; 130μm are needed and manufacturers are focusing on copper (Cu) pillars to achieve tighter pitches. Therefore, there is a need to investigate the effect of replacing solder bumps with Cu pillars on the fracture behavior of the BEoL dielectric. This provides the impetus for this work. In this study, a 3D finite element (FE) fracture analysis is performed to demonstrate the thermo-mechanical response of the BEoL region of a flip chip package with Cu pillars (CuP). Crack propagation in the low-k layers is analyzed under the loading when the die is attached to the substrate (reflow). J-integral obtained from the FE analysis is utilized to quantify the impact of replacing solder bumps with Cu-pillars in future high density portable devices.