A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

A 0.21 /spl mu/m/sup 2/ 7/sup F/2 trench capacitor DRAM cell with a locally-open globally-folded dual bitline has been fabricated using a 175 nm groundrule. This cell features a trench capacitor, a self-aligned trench-to-diffusion buried strap in direct proximity to the array transistor, shallow-trench device isolation (STI), a self-aligned poly-plug bitline contact, and two-levels of bitline wiring, both formed using a dual damascene process.