A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization

In this work a 3.97 /spl mu/m/sup 2/ 6T CMOS SRAM bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization. This 0.20 /spl mu/m process technology is suitable for stand-alone SRAM applications as well as embedded applications such as digital signal processors. A stable bitcell operation has been demonstrated for power supply (Vdd) of 1.8 V. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.65 /spl mu/m.