An 18b 20KHz Dual /spl Sigma/spl Delta/ A/D Converter

Sigma-delta noise shaping has been used in A/D converters to increase dynamic range without increasing the accuracy demands placed on individual components. Stable, signal-bit higher-order loops have been designed that extend the dynamic range of ΣΔ converters while retaining low component accuracy requirements. This paper describes a dual, 20k Hz bandwidth, 18b ΣΔ ADC with an oversampling ratio of 64 and a noise floor that is 105dB below full scale. The converter is implemented on two chips: a 10V 3μm CMOS modulator chip, and a 5V 1.5μm CMOS decimator chip.