A 17ns 4Mb CMOS DRAM Using Direct Bit-line Sensing Technique

This 17ns pure CMOS 4Mb DRAM achieves fast access using a direct bit-line sensing technique with two-stage current mirror read-out amplifier, supported by non-multiplexed-address configuration.1.2 A selected current mirror read-out amplifier is activated by a column decoder output (CSL), before the selected word line (WL) rises, and then detects the small signal on a bit-line pair immediately after the WL rise. Circuit parameter optimization and careful pattern layout for the current mirror amplifier result in high sensitivity.