A 17ns 4Mb BICMOS DRAM

This 0.8μm 4Mb BiCMOS DRAM achieves 17ns chip enable. BiCMOS technology is employed because it enhances DRAM performance, as shown in previous reports of a 23ns 1Mb BICMOS SRAM. Access time is improved by use of circuits, such as a dynamic pull-down address buffer, noise-immune cascode amplifier, and an offset-cross output circuit, which enables the level converter to drive the output transistor directly. Figure 1 shows a comparison of access time of the 23ns 1Mb BiCMOS DRAM and this chip.