A 10ns 4Mb BICMOS TTL SRAM

In high-density TI'L-VO SRAM, BiCMOS is gaining acceptance for applications requiring fast access. Access times near and below lOns have been reported.1,2 This 4Mb ( 4Mxl/1Mx4) BiCMOS TI'L-VO SRAM has typical access time of lOns and active power dissipation of 450mW at 50MHz. The density and speed were achieved using a 0.5µm CMOS quadniple-polysilicon, double-metal process for the cell array and a 0.8µm BiCMOS process for the peripheral circuits. To achieve lOns access time, two-stage sense amplifiers and a p-n MOS cross-coupled level converter (CLC) which converts the output of a bipolar differential amplifier to the CMOS output are used.