A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM

A 512kb CMOS ECL SRAM with 2ns cycle and 4ns access for fully-random read/write operations uses a 0.8μm CMOS technology having a 0.5μm L
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The 2ns cycle time is obtained through more aggressive use of pipelining than previously reported. The pipelining is transparent to the user.