A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance

A block diagram of the direct digital synthesizer (DDS) chip is shown in Figure 1. Sine waves are generated in this design by accumulating a digital value in a periodically overflowing 2's- complement accumulator. The output of this accumulator serves as the phase argument for the sine function. A new sine sample is calculated every clock cycle from a 15b truncated version of this phase argument and is output with 12b precision to an off-chip D/A. A frequency resolution of F
_clk
/2
³²
is obtained by using a 32b phase accumulator. The output frequency of the DDS chip is related to the contents of the frequency control register by: F
_out
= F
_clk
(F /2
³²
+ 1/2
³³
). Therefore at a clock rate of 150MHz the DDS can be tuned in steps of .035Hz from dc to 75MHz. Switching speed at this clock rate is 6.7ns with a tuning latency of 13 pipeline delays.