Design and implementation of FPGA-based transmitter memory management system

FPGA is the first choice for developing the prototype system and the IP cores. Many existing network protocols are developed as IP cores, for example, the ethernet MAC open core. In this paper, an FPGA-based memory management system is proposed for the MAC protocol IP core, to facilitate the memory status acquisition and to support the functions in term of receiving packets from the upper layer, transmitting aggregated packets, and selectively re-transmitting the failed packets. The basic idea is to separate the packet management function from the packets store function of the memory system, where each buffer descriptor in the packet management block corresponds to a packet buffer in the packet store block. The design philosophy and the implementation details are presented.