FPGA implementation of a scalable shared buffer ATM switch

This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4/spl times/4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz.