A CMOS 260 Mbps read channel with EPRML performance

In this paper, the read channel architecture for a 260 Mbps read channel far magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35 /spl mu/m DPTM CMOS and dissipates 1.3 W max at 260 Mbps.