Non-precharged bit-line sensing scheme for high-speed low-power DRAMs

Various proposals have been made and implemented for improving the bandwidth of the DRAM Input/Output interface. However, random access speed, which has limited DRAM total performance, has not been improved enough. Some proposals have been made to improve it, such as over-driving the power supply voltage for sense amplifiers, and amplifying the signal on bit-lines. These schemes, however, have suffered from increased power dissipation. This paper proposes a Non-Precharged Bit-line Sensing (NPBS) scheme in which data access is performed without precharging bit-lines. This realizes both an improvement of random access speed and a reduction of power dissipation. Also, we propose a power reduction scheme for the memory system named Initial Same Data Write (ISDW). In combination with the NPBS, the power is effectively reduced when part of a memory system is not used.