Improved two-step clock-feedthrough compensation technique for switched-current circuits

A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S/sup 2/I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.