MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump

The design of CPU (central processing unit) chips for the MARS project is described. They are the IFU (instruction fetch unit), IPU (integer processing unit), and LPU (list processing unit). The IFU is devised to interleave instruction fetch and execution, and thus to achieve coordinated execution among datapath chips. The IPU is the main computing engine for integer operations and operand address calculation. By using dual-instruction buffers, a reserved phase for branch/jump target fetch, and instruction decode peeping, the architecture can support almost-zero-delay branching and super-zero-delay jump. The LPU handles a Lisp runtime environment, dynamic type checking, and fast list access. In this architecture, the critical path of complex register file access and ALU operation is distributed over the LPU and IPU, and list tracing can be executed quickly by the nondelayed car or cdr instructions.<>