A low power GPS/Galileo/GLONASS receiver in 65nm CMOS

A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm
²
including bonding PAD. The system noise figure (NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.