Proposal of 130nm-60V rated fully isolated LDNMOS with double Epi process

In this paper, we developed 60V rated fully isolated LDNMOS which can be available under negative bias condition. Double epi process for obtaining higher BVdss, PBL (p+ buried layer) for retarding punch through and NBL-2 (n+ buried layer) for a role of electrically connecting NBL-1 are adopted to achieve 60V rated fully isolated LDNMOS. This optimized device has characteristics of Ron.sp 55mohm∗mm
²
and BVdss 66V. We could also develop 90V rated high side LDMOS with Ron.sp 210mohm∗mm
²
and BVdss 110V through this same double epi process.