Shared memory implementation of a parallel switch-level circuit simulator

Circuit simulation is a critical bottleneck in VLSI design. The paper describes the implementation of an existing parallel switch level simulator called MIR-SIM on a shared memory multiprocessor architecture. The simulator uses a set of three different conservative protocols: the null message protocol; the conditional event protocol and the accelerated null message protocol; and combinations of the preceding two algorithms. The paper describes the implementation of these protocols to exploit shared memory features, measures their relative performance for a set of six benchmark circuits ranging in size from 3000 to almost 70000 transistors, and compares the speedup obtained by each of the three protocols.