FRAM sense amplifier with compensation for random and systematic offset

Sense Amplifiers have always been an integral part of an embedded memory design and operation. The decreasing process size, appetite for speed, low power, and smaller area all contribute to increased Sense Amplifier (SA) offset. In FRAM technologies, factors such as bitcell scaling, thermal depolarization [2], solder reflow processes [1], and state-dependent imprinting [2] all contribute to decreased signal margin available to the SA. Therefore, increase in SA offset coupled with decrease in signal margin translates into loss of yield and reliability. This paper introduces a modified SA circuit design that through introduction of localized and intentional asymmetrical capacitive loading, on state defining nodes, is shown to reduce the sample sigma and range of the SA's offset, improving the yield.