Environment dependence of analog matching and design-process optimization on a 28LP SoC technology for smart mobile devices

Mismatch of analog circuits designed for mobile devices are studied with nanoprobing, pattern density, and inline monitoring using a 28LP SoC technology. Active layer density was found to be the root cause of high mismatch variation. Design guidelines, along with an interleaved design, are shown to improve mismatch for a given process flow.