A parasitics extraction and network reduction algorithm for analog VLSI

A transmission line model for the extraction of circuit parasitics in integrated circuits is presented. This model is shown to give a better account of the DC and aC characteristics of interconnects than models incorporating exclusively the R or C components. A network-reduction technique that is used to simplify the extracted RC network at user-specified accuracies to manageable complexities, especially for large VLSI circuits, is also discussed. The model and circuit reduction algorithms are applied to practical sample circuits and results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy by these methods are given.<
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