Two novel designs of multi-phase clocked ultra-high speed time counter on FPGA for TDC implementation

The shifted clock sampling method is an effective time interpolation scheme for a large channel count TDC system on an FPGA as its advantages of small logic resource consumption, uniform bin widths, insensitivity to temperature and power supply voltage. The bottleneck of the scheme is the clock synchronization if one wants to achieve comparable TDC resolution with the delayed data sampling method. In this paper we propose two novel designs, called multi-phase clocked ultra-high speed time counter, to overcome the bottleneck so that the potential of the clock management resource of today's FPGA could be fully utilized. With the solutions, the implementation of a large channel count TDC with a high resolution on an FPGA is very promising.