Parallel implementations of transition fault simulation on computational RAM (C/spl middot/RAM)

Stuck-at faults and transition faults model how physical defects can disturb the proper operation of digital circuits. Two transition faults that are commonly considered are gate delay faults, where an unexpected lumped delay is associated with a gate input or output, and CMOS transistor stuck-open faults, where low-to-high or high-to-low output transitions cannot occur for certain input combinations to a gate. Fault simulation is the computationally intensive process of determining the proportion of faults that would be detected if a given sequence of test patterns were to be applied to a given circuit. The paper describes how a conventional parallel fault simulation algorithm for stuck-at, gate delay and stuck-open faults was adapted to exploit the massive single instruction multiple data (SIMD) parallelism available in the computational RAM (C/spl middot/RAM) architecture.