Design and processing of various configurations of silicon pixel detectors for high irradiation tolerance up to 6/spl times/10/sup 14/ n/cm/sup 2/ in LHC application

Various new configurations of silicon pixel detector have been designed and are in prototype production. The material selection and detector design are aimed to produce silicon detectors with radiation tolerance up to 6/spl times/10/sup 14/ n/cm/sup 2/ (or 4/spl times/10/sup 14/ /spl pi//cm/sup 2/) in LHC environment, which corresponds to a net increase (with long term anneal) of space charge of about 4.2/spl times/10/sup 13/ cm/sup -3/. The configuration of n/sup +//n/p/sup +/, with multi-guard-rings structure for high voltage (up to 300 volts) operation, has been used for the purpose to make the detector insensitive to space charge sign inversion. The material selection of medium resistivity (1.9k /spl Omega/-cm) n-type silicon has been made to try a new solution in extending detector lifetime: it should be the first step toward the use of low resistivity silicon, to prevent type inversion. The traditional configuration of p/sup +//n/n/sup +/, with multi-guard-ring structure and n-type material, has also been used with the same layout, to get a comparison. It is shown that the fabrication of n+n/p+ pixel detectors requires eight mask steps, while just four mask steps are required for the p/sup +//n/n/sup +/ configuration.