Structure design and reliability assessment of double-sided with double-chip stacking packaging

Recently, consumer electronics demand has been geared towards lightweight, high efficiency, and small form factor devices. These characteristics can be accomplished by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. Regarding to the proposed structure, the finite element (FE) model is established to investigate the actual thermo-mechanical behavior during thermal cycling loading. The suitable geometry design of buffer layer and carrier can enhance the reliability of solder joint. The application of soft filler and passivation materials can increase the predicted fatigue life to more than 2,500 cycles. However, the high coefficient of thermal expansion (CTE) of soft filler material will induce significant deformation and excessive strain on the trace layer. Based on the above simulation methodology and life prediction model, the development of the proposed structure can be optimized within a feasible time. This effective methodology is necessary in the electronic packaging industry to reduce time-to-market and fabrication cost when a new packaging structure is being developed.