Design of PID controller for disturbance rejection: a genetic optimization approach

We present a PID controller design method for disturbance rejection. The method is based on the minimization of the integral of time multiplied-squared error (ITSE) subject to a disturbance rejection constraint of the type H/sub /spl infin// norm. A design method using genetic optimization with two real-coded GAs, appropriate operators and penalty function is proposed for the solution of the constrained optimization problem. Simulation results are given to illustrate the new approach, and to show the validity of the proposed design method.