Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage

The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.