Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures

The statistical error propagation method is used to analyze the parametric variance of current gain and breakdown voltage in bipolar analog integrated circuits in terms of the relative variance of four process factors; emitter sheet resistance, based sheet resistance, buried layer sheet resistance, and epitaxial thickness. The dominant level of device parameter variance and the dominant process factors to which the device is sensitive are identified, using simple test structures, thereby facilitating the tightening of variability of the device parameter. This technique is useful for integrating the device data into the process control analysis and separating the effects of the critical process factors in a fabrication environment. How the process variance of analog integrated circuits is improved by this method is demonstrated.<
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