A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS

This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array technique is utilized to tolerate offset mismatch between the coarse and fine stages. The level-shift technique is used to accelerate the comparator. The ADC in 40-nm CMOS obtains 5.6 and 4.9 effective numbers of bits at Nyquist with the conversion rate of 800 MS/s and 1 GS/s, respectively. It consumes 5.3 mW at 1 GS/s and achieves a figure of merit of 180 fJ/ conversion-step. The core circuit occupies an area of 0.009 mm
²
.