Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

Deep submicron elevated source/drain (S/D) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering /spl Delta/V/sub t/ (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the S/D extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area.