Low power signal processing architectures using residue arithmetic

Recent trends like increasing operating frequencies, larger die sizes and demand for greater portability make power reduction a hard taskmaster. It is acknowledged that the greatest returns come from optimization at the architectural and technology level. We present, for the first time, residue architectures that reduce the power by more than 70% without changes in technology. This reduction is achieved without sacrificing performance and with minimal sacrifice in area (less than 60%). The key to such low power solutions is trading-off the speed gained by parallelism for lower power. Existing proposals that achieve similar trade-offs demand an area increase of more than a factor of two and also increased control complexity. Other benefits of using residue arithmetic for low power is the significant reduction in peak current and increased design locality. The role of the number of computations per forward (or reverse) conversion in determining the power characteristics of the system are also analyzed and explained. The effectiveness of the methodology is illustrated using a system that extracts a 256-point FFT of the input signal.