Investigation of Key Technologies for Poly-Si/TaN/HfLaON/IL ${\rm SiO}_{2}$ Gate-Stacks in Advanced Device Applications

We demonstrated for the first time integration of a poly-Si/TaN/HfLaON/IL SiO
₂
gate-stacks into high-performance sub-30-nm nMOSFETs using a gate-first process flow successfully. The properties of TaN/HfLaON/IL SiO
₂
gate-stacks were studied. The results showed that the HfLaON gate dielectric material exhibited excellent thermal stability and electrical characteristics. A three-step dry etching method used to etch poly-Si/TaN/HfLaON/IL SiO
₂
gate-stack was proposed to provide an effective pathway for patterning the complex gate-stacks. At V
_DS
=V
_GS
=0.9 V, the drive current I
_ON
of 410 μA/μm was achieved at an OFF-state leakage current I
_OFF
of 180 nA/μm. The threshold voltage of saturation extracted at I
_DS
of 3 μA/μm was 0.14 V. The subthreshold slope of 92 mV/decade and drain induced barrier lowering of 93 mV/V were obtained.