Implementation of a Quad-Phase Lowpass Delta-Sigma Modulator in a 65 nm CMOS Technology

In this work the concept and implementation of a lowpass DeltaSigma based transmitter is presented. The conventional LPDeltaSigma approach is enhanced by increasing the number of phase signals which are modulated from two to four signals. On one hand this decreases the quantisation noise on the other hand the speed requirements for the upconversion increase respectively. An appropriate topology for this concept is sketched and an implementation with focus on the upconversion multiplexer is shown. The feasibility of the topology is verified by measurements on an FPGA and shows a noise reduction between 3 dB and 6 dB. Following this, the concrete implementation is examined with post layout simulations. Finally the implementation is fabricated in an 65 nm CMOS technology