Accurate logic simulation models for TTL totempole and MOS gates and tristate devices

The two logic values, 0, 1, and the unknown, are not sufficient for accurately simulating the behavior of TTL totempole and MOS gates and tristate devices. Furthermore, the classical fault modes (output stuck and input open) are not sufficient to cover the faulty behavior of MOS devices. A previous solution to the simulation modeling required the addition of pseudo gates, which have no physical meaning. This paper develops methods of modeling fault-free and faulty tristate devices for logic simulation. The model does not require any additional circuitry, but the existence of a simulator capable of simulating any number of logic values is assumed.