A novel 3D crossbar-based chip multiprocessor architecture

Moore's law still offers more transistors to fit per die unit area and this leads to the expectation of having thousands of cores fit on a single chip soon. Thus, Network-on-Chip proved to be a successful approach to accommodate this increasing number of cores on chip. However, the previously proposed 2D architectures still lack the scalability to more than few tens of cores where the inefficiencies of those architectures come in the form of long interconnect delays leading to performance degradation and high power consumption due to long wires. Fortunately, the rapid advances in 3D die-stacking technology as a promising trend for the state of the art high-performance processor designs raised the possibilities of having new approaches towards a scalable interconnection network. Thus, in this paper, we propose a novel 3D crossbar-based architecture that separates cores from cache modules in different 3D stacked dies.We introduce area model of the adopted crossbar and analyze the scalability of the proposed architecture up to 1024 communicating entities; cores and L2 cache banks.