An avalanche current path optimizing method for superjunction MOSFET to enhance unclamped inductive switching capability

The internal parasitic bipolar transistor plays an important role in the unclamped inductive switching (UIS) failure of superjunction MOSFET. To suppress the activation of parasitic transistor, an innovative structure was proposed which features a P-island with relatively high doping concentration at the top of P-column and a trench-type P+ contact. The avalanche point is localized at the P-island and the avalanche current path is away from the N+ source/P-body junction. The mechanism of the proposed structure was thoroughly investigated and the optimizing method of the P-island was also discussed. Simulations show that the avalanche current path optimizing strategy can achieve a good trade-off between UIS capability and breakdown characteristics.