IEEE Standard for Design and Verification of Low-Power Integrated Circuits - Redline

A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit http://standards.ieee.org/about/get/index.html for more details.)