Spatial and temporal stability of vision chips including parasitic inductances and capacitances

There are two dynamics issues in vision chips: (i) the temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. In this paper we consider parasitic inductances as well as parasitic capacitances for a network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases.