Impact of Stress Mode on Stochastic BTI in Scaled MG/HK CMOS Devices

Stochastic bias temperature instability (BTI) modeling has gained importance for scaled metal gate/high- k CMOS devices to ensure SRAM circuit functionality. In this letter, we discuss the impact of the BTI stress mode on the ΔV
_T
distribution and the time evolution of VT in small and large area CMOS devices. It is shown that the stress mode has strong impact on the evolution of the threshold voltage distribution in small area devices leading to an increase in the σ-value for constant overdrive stress, whereas no change is observed for constant voltage stress. Since CMOS circuits share the supply voltage, the constant voltage stress σ-values are relevant and thus, the reliability guidance for future CMOS design should be based on constant voltage stress.