Substrate noise issues in mixed-signal chip designs using Spice

As digital clocking frequencies continue to increase, substrate noise is fast becoming a critical issue for mixed-signal chip designers. However, current methods for directly modelling the noise in realistically-large Spice designs are impractical, due to numerical instabilities. In this paper, partial modelling of the substrate is introduced and shown to be an efficient and viable approach. The technique is validated using a testbed circuit. Commonly-used noise-reduction schemes are briefly compared and P+ guard-rings are used to reduce the noise in an example circuit.