A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm
²
resulting in the best performance-area trade-off system presented up-to-date.