A 4.2GS/s 4-bit ADC in 45nm CMOS technology

In this paper an analog to digital converter architecture is introduced. The proposed design is based on a mixed approach of flash type ADC and SAR type ADC. This design offers lesser number of comparators and so low power consumption with much less circuit complexity in comparison to conventional flash ADC architecture. Based on the proposed idea, a 4-bit ADC is simulated in Cadence virtuoso Tool using 45nm CMOS technology with power supply voltage of ± 0.6 V. Maximum sampling speed of ADC is achieved as 4.2 GS/s. The ADC consumes 72μW of power. The measured INL and DNL are 0.40 LSB and 0.42 LSB respectively.