On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security

This paper presents new power analysis attack (PAA) countermeasures for nanoscale cryptographic devices. Specifically, three circuit level architectures called partial decoupling architecture, full decoupling architecture, and randomized switch box architecture are developed and analyzed. The architectures' primary feature is the use of on-chip nMOS gate capacitors as intermediate power storage elements to decouple the power supply from internal low-power modules processing sensitive data. The proposed countermeasures are algorithm independent and allow different tradeoffs between security protection and the incurred overheads. Test benches of the proposed architectures were simulated in 65-nm TSMC CMOS technology. A correlation PAA was performed for each test bench targeting a custom implementation of the advanced encryption standard subbytes operation. All architectures were found to resist the correlation PAA at the power supply, with the more complex architectures also offering protection against invasive attacks. The success value indicator was used to analyze the effectiveness of the countermeasures. It was found that all architectures provided a negative value at the power supply, showing protection against PAAs. We demonstrate that the use of nMOS gate capacitors can help to increase security and present a feasibility analysis focused on the needed decoupling capacitances.