Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory

We extracted final
$\Delta V_{\rm th}$
, time constant, and activation energy
$(E_{a})$
of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of
$V_{{\rm th}}$
cumulative probability distribution. As a result, we confirmed that at lower P level, the final
$\Delta V_{{\rm th}}$
of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final
$\Delta V_{{\rm th}}$
of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger
$E_{a}$
at high P level, whereas the
$E_{a}$
of detrapping mechanism decreases because of barrier lowering effect.