Complete stress state measurements in chip on board packages

In this work, die stresses in wire bonded chip on board (COB) packages have been measured using special Si(111) stress test chips. The test die contained an array of optimized eight-element dual polarity piezoresistive sensor rosettes, which are uniquely capable of evaluating the complete stress state (6 stress components) at points on the surface of the die. Sensor resistance measurements were recorded before packaging, after die attachment, and throughout the encapsulant cure process. Using the appropriate theoretical equations, the stresses at sites on the die surface have been calculated from the raw sensor resistance data. Also, preliminary three-dimensional nonlinear finite element simulations of the chip on board packages were performed and the stress predictions were correlated with the experimental test chip data.