Effects of buried layer geometry on characteristics of double polysilicon bipolar transistors

Dependences of electrical characteristics of double polysilicon transistors on n/sup +/ buried islands (subcollector) are examined. By simply modifying layouts of the buried island, the Early voltage (V/sub A/), collector-to-emitter breakdown voltage (BV/sub CEO/), and /spl beta//spl times/V/sub A/ product of transistors are increased from 42, 5.6, and 3070 V to 61, 6.7, and 3820 V, respectively, while the peak cutoff frequency at a V/sub CE/ of 1.5 V is decreased from around 21 to 17 GHz. Exploiting these results, it may be feasible to inexpensively integrate transistors with better f/sub T/-BV/sub CEO/ and f/sub T/-V/sub A/ tradeoffs for analog and power handling characteristics along with transistors optimized for high-speed operation. These results also indicate that the buried island geometry control could be an issue for controlling electrical characteristics for scaled bipolar transistors.