A data-transition look-ahead DFF circuit for statistical reduction in power consumption

A new data-transition look-ahead DFF (DL-DFF) that reduces the power consumption of CMOS LSI's is proposed. The power consumption is reduced in accordance with the data-transition probability. The main feature of the DL-DFF is that the clock signal is deactivated when there are no data transitions. This reduces the power consumption when the data-transition probability is low. The power consumption of a DL-DFF is compared to that of a conventional one by measuring a test chip fabricated using a 0.25-/spl mu/m CMOS/SIMOX process. It is found that a DL-DFF consumes less power than a conventional one when the data-transition probability is under 60%. For example, when the data-transition probability is 25%, it consumes 29% less power. Moreover, some suitable applications of a DL-DFF are presented.