Beamforming complexity reduction methods for low-cost FPGA-based implementation

This paper presents two methods for reducing complexity of dynamic receive beamforming in order to be implemented on a single field-programmable gate array (FPGA) with 500K gates. These methods apply windows to divide each scanline into segments and each segment has its own focus at the center. One method uses constant window size and the other applies dynamic window size that equalizes the off-focus beamforming delay errors among the windows at different depths. The frame rates and the axial and laterial beam profiles of a point scatterer are compared using simulated and experimental echo signals.